The present invention relates to a technology for relieving defects in a memory cell array in an electrically programmable nonvolatile semiconductor memory device, to a technology for relieving defects that are produced after the memory device is mounted on a board by using a redundancy memory element, and to a data processor capable of repairing defects in a memory cell array that are produced after the memory device is mounted on a board such as a technology that can be effectively adapted to a single-chip microcomputer that contains an electrically rewritable flash memory.
The present inventors have studied about relieving defects in the memory cell array of a nonvolatile semiconductor memory device such as an EEPROM and flash memory. In a conventional technology for relieving defects in a memory cell array using a redundancy memory element, the address of the memory element that is to be relieved is made programmable by, for example, selectively melt-cutting fuses. This technology can, be adapted to initial defects that can be detected in the production but cannot be adapted to relieving defects after mounted on a circuit board as a finished product. The present inventors have discovered the necessity of relieving defects that are produced with the passage of time after mounted since the characteristics of the memory elements in the electrically rewritable nonvolatile memory device deteriorate with an increase in the number of times of rewriting. There has been proposed a semiconductor memory device equipped with a function of detecting, and correcting errors, such as ECC (Error Checking and Correcting circuit) from the standpoint of improving reliability. For this purpose, however, a memory capacity larger than an ordinary capacity is necessary for the error check bit, limiting even events that can be relieved. Therefore, the function fails to serve as means for effectively relieving defects that are produced while the device is being practically used.
Japanese Patent Laid-Open No. 1398/1991 discloses a technology which is related to a one-chip microcomputer containing an EPROM and further containing a circuit which changes the EPROM that happens to become defective to an auxiliary EPROM. Japanese Patent Laid-Open No. 107500/1987 discloses a technology which transfers defective address data stored in a nonvolatile memory element to the latch in a decoder when the power is on and changes the decoder when a defective address is selected. According to Japanese Patent Laid-Open No. 118999/1990 which is concerned with an EEPROM-containing microcomputer, the defective address of the EEPROM is stored in a particular area, the CPU checks the defective address when an access is made to the EEPROM, and a substitute area is used when the check reveals the agreement. Japanese Patent Laid-Open No. 162798/1991 discloses a technology by which defective address data to be relieved are stored in a particular memory element of the memory cell array, and access is changed to a redundancy memory element according to data read out from the above memory element in response to an address that is read out.